Harmonics and Common Mode Voltage Reduction in Multilevel SPWM Technique

被引：0

作者：

Chaturvedi, P. K. ^{[1
]}

Jain, Shailendra ^{[1
]}

Agrawal, Pramod ^{[2
]}

机构：

[1] Natl Inst Technol, Dept Elect Engn, Bhopal, India

[2] Indian Inst Technol, Dept Elect Engn, Roorkee, Uttar Pradesh, India

来源：

PROCEEDINGS OF THE INDICON 2008 IEEEE CONFERENCE & EXHIBITION ON CONTROL, COMMUNICATIONS AND AUTOMATION, VOL II | 2008年

关键词：

Common Mode Voltage; Harmonics; Multilevel Inverter;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Conventional 2-level PWM inverters generate high dv/dt and high frequency common mode voltages which is very harmful in electric drives applications. It may damage motor bearings, conducted electromagnetic interferences, and malfunctioning of electronic equipments. This paper presents the simple methods to control the harmonics as well as common mode voltages in multilevel inverters using different structures of sine-triangle comparison method such as Phase Disposition (PD), Phase Opposition Disposition (POD), and Common Mode Voltage off-set voltage addition method. Simulation results obtained in Matlab/Power System Blockset toolbox confirms the effectiveness of these simple methods to control common mode voltages. Experimental results presented have been obtained using dSpace 1104.

引用

页码：447 / +

页数：3

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