A novel integration of STT-MRAM for on-chip hybrid memory by utilizing non-volatility modulation

被引：10

作者：

Park, J. -H. ^{[1
]}

Lee, J. ^{[1
]}

Jeong, J. ^{[1
]}

Pi, U. ^{[1
]}

Kim, W. K. ^{[1
]}

Lee, S. ^{[1
]}

Noh, E. ^{[1
]}

Kim, K. ^{[1
]}

Lim, W. C. ^{[1
]}

Kwon, S. ^{[1
]}

Bae, B. -J. ^{[1
]}

Kim, I. ^{[1
]}

Ji, N. ^{[1
]}

Lee, K. ^{[1
]}

Shin, H. ^{[1
]}

Han, S. H. ^{[2
]}

Hwang, S. ^{[2
]}

Jeong, D. ^{[1
]}

Lee, J. ^{[1
]}

Oh, S. C. ^{[1
]}

Park, S. O. ^{[1
]}

Song, Y. J. ^{[2
]}

Jeong, G. T. ^{[2
]}

Koh, G. H. ^{[1
]}

Hyun, S. ^{[1
]}

Hwang, K. ^{[1
]}

Nam, S. W. ^{[1
]}

Kang, H. K. ^{[1
]}

Jung, E. S. ^{[2
]}

机构：

[1] Samsung Elect Co Ltd, Semicond R&D Ctr, Hwaseong, South Korea

[2] Samsung Elect Co Ltd, Foundry Business, Giheung, South Korea

来源：

2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年

关键词：

D O I：

10.1109/iedm19573.2019.8993614

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate a novel way of integrating STT-MRAM for on-chip hybrid memory which exhibits either features of high-retention or high-speed implemented in separate zones in a single chip. For satisfying high-temperature retention requirement, tailored MTJs are shown to support > 10 year retention at 220 degrees C. For high-speed operation, critical improvements have been made in terms of TMR, short fail probability, overdrive and write error rate. The new integration provides a manufacturable way of combining diverse memory components by modulating nonvolatility of STT-MRAM without affecting within-chip distributions of critical properties.

引用

页数：4

共 42 条

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