ESD protection design for I/O libraries in advanced CMOS technologies

被引：9

作者：

Semenov, Oleg ^{[1
]}

Somov, Sergei ^{[1
]}

机构：

[1] Freescale Semicond LLC, Res Lab, Moscow 124489, Russia

来源：

SOLID-STATE ELECTRONICS | 2008年 / 52卷 / 08期

关键词：

electrostatic discharge (ESD); failure mechanisms; ESD devices; I/O architecture;

D O I：

10.1016/j.sse.2008.05.008

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

There are several approaches for ESD protection of integrated circuits. This paper provides practical guidelines to I/O library designers to choose the right methodology for ESD protection of I/O libraries in advanced CMOS technologies. Guidelines are provided predominantly for low-voltage I/O libraries that are commonly used for general purpose interfaces and industrial low-voltage interfaces such as DDR, MLB, USB, etc. Additionally, some general background issues of ESD protection methodologies used in the industry are considered. This paper is focused on HBM and MM ESD protection solutions. Special CDM ESD protection solutions are not considered. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1127 / 1139

页数：13

共 50 条

[31] Latch-up Free ESD Protection Design With SCR Structure in Advanced CMOS Technology
Wang, Chang-Tzu
Tang, Tien-Hao
Su, Kuan-Cheng
2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2011,
[32] Advanced CMOS Technology Challenges for Robust ESD Design
Chen, Shih-Hung
2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
[33] LVSMOS: an I/O-cell-friendly ESD and latchup robust structure for CMOS submicron technologies with compact cell design
Lin, Shi-Tron
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Proceedings of Technical Papers, 2007, : 58 - 59
[34] ElectroStatic Discharge (ESD) one real life event : Physical Impact and protection challenges in advanced CMOS technologies
Galy, Ph.
2014 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), 2014, : 31 - 34
[35] ESD protection design in a-IGZO TFT technologies
Scholz, M.
Steudel, S.
Myny, K.
Chen, S.
Boschke, R.
Hellings, G.
Linten, D.
2016 38TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2016,
[36] MOSFET ESD breakdown modeling and parameter extraction in advanced CMOS technologies
Vassilev, Vesselin
Lorenzini, Martino
Groeseneken, Guido
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (09) : 2108 - 2117
[37] ESD protection design for mixed-voltage I/O interfaces - Overview
Ker, Ming-Dou
Lin, Kun-Hsien
2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS, 2005, : 493 - 498
[38] Design optimization of ESD protection and latchup prevention for a serial I/O IC
Huang, CY
Chen, WF
Chuan, SY
Chiu, FC
Tseng, JC
Lin, IC
Chao, CJ
Leu, LY
Ker, MD
MICROELECTRONICS RELIABILITY, 2004, 44 (02) : 213 - 221
[39] Provide ESD protection for I/O ports
Fox, B
Parvarandeh, P
EDN, 1997, 42 (12) : 137 - &
[40] ESD protection with BIMOS transistor for Bulk & FDSOI advanced CMOS technology
Galy, Ph
Bourgeat, J.
Lim, T.
Fenouillet-Beranger, C.
Golanski, D.
2013 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), VOLS 1-2, 2013, : 171 - 174

← 1 2 3 4 5 →