Novel back end-of-line process scheme for improvement of negative bias temperature instability lifetime

被引:1
|
作者
Ho, WJ
Park, SH
Kim, DS
Han, IS
Lee, HD [1 ]
Kim, JY
Park, YB
Kim, DB
机构
[1] MagnaChip Semicond, Div Technol, Cheongju 361725, South Korea
[2] Chungnam Natl Univ, Dept Elect Engn, Taejon 305764, South Korea
关键词
negative bias temperature instability; NBTI; passivation layer; BEOL process; hot carrier;
D O I
10.1143/JJAP.45.2455
中图分类号
O59 [应用物理学];
学科分类号
摘要
A novel back end-of-line (BEOL) process scheme is proposed to improve negative bias temperature instability (NBTI) characteristics through the characterization of the impact of each BEOL process on NBTI of p(+) gate metal oxide semiconductor field-effect transistor (PMOSFETs). It is demonstrated that NBTI is strongly dependent on the plasma enhanced nitride (PE-SiN) passivation film and H, sintering anneal. A new process scheme of N-2 annealing instead of H, annealing prior to PE-SiN deposition is proposed and proven to be highly efficient in improving NBTI without degradation of device performance and n(+) gate metal oxide semiconductor (NMOS) hot carrier lifetime.
引用
收藏
页码:2455 / 2458
页数:4
相关论文
共 43 条
  • [1] Body to ground improvement at trim and form machine in end-of-line process
    Mohtar, M. H.
    Maidin, S.
    [J]. PROCEEDINGS OF MECHANICAL ENGINEERING RESEARCH DAY 2015, 2015, : 69 - 70
  • [2] Negative Bias Temperature Instability Lifetime Prediction: Problems and Solutions
    Ji, Z.
    Hatta, S. F. W. M.
    Zhang, J. F.
    Ma, J. G.
    Zhang, W.
    Soin, N.
    Kaczer, B.
    De Gendt, S.
    Groeseneken, G.
    [J]. 2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
  • [3] High Voltage Device Negative Bias Temperature Instability Improvement with Different Process Conditions
    Sim, P. C.
    Koo, S. S.
    Pal, D. K.
    [J]. CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011), 2011, 34 (01): : 967 - 972
  • [4] Negative Bias Temperature Instability Characterization and Lifetime Evaluations of Submicron pMOSFET
    Hatta, S. F. Wan Muhamad
    Hussin, H.
    Soon, F. Y.
    Wahab, Y. Abdul
    Hadi, D. Abdul
    Soin, N.
    Alam, A. H. M. Zahirul
    Nordin, A. N.
    [J]. 2017 IEEE SYMPOSIUM ON COMPUTER APPLICATIONS & INDUSTRIAL ELECTRONICS (ISCAIE), 2017, : 206 - 211
  • [5] Improvement of Negative Bias Temperature Instability by Stress Proximity Technique
    Yang, Jian Bo
    Chen, T. P.
    Gong, Ying
    Tan, Shyue Seng
    Ng, Chee Mang
    Chan, Lap
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (01) : 238 - 243
  • [6] Effect of the process flow on negative-bias-temperature-instability
    Scarpa, A
    van Marwijk, L
    Cacciato, A
    Ballarin, F
    [J]. 2003 8TH INTERNATIONAL SYMPOSIUM ON PLASMA- AND PROCESS-INDUCED DAMAGE, 2003, : 142 - 145
  • [7] Negative-bias temperature instability cure by process optimization
    Scarpa, Andrea
    Ward, Derek
    Dubois, Jerome
    van Marwijk, Leo
    Gausepohl, Steven
    Campos, Richard
    Sim, Kwang Ye
    Cacciato, Antonio
    Kho, Ramun
    Bolt, Mike
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (06) : 1331 - 1339
  • [8] Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability
    Hong, Hyejeong
    Lim, Jaeil
    Lim, Hyunyul
    Kang, Sungho
    [J]. ACM COMPUTING SURVEYS, 2015, 48 (01)
  • [9] Accurate negative bias temperature instability lifetime prediction based on hole injection
    Teramoto, Akinobu
    Kuroda, Rihito
    Sugawa, Shigetoshi
    Ohmi, Tadahiro
    [J]. MICROELECTRONICS RELIABILITY, 2008, 48 (10) : 1649 - 1654
  • [10] Difference analysis method for negative bias temperature instability lifetime prediction in deeply scaled pMOSFETs
    Liao, Yiming
    Ji, Xiaoli
    Zhang, Chengxu
    Huang, Xiaolin
    Xu, Yue
    Yan, Feng
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 2017, 56 (04)