An innovative technique to examine gate oxide anomaly for failure analysis

被引：0

作者：

Chan, HG

Lit, YK

机构：

来源：

ICSE '96 - 1996 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS | 1996年

关键词：

D O I：

10.1109/SMELEC.1996.616445

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new and innovative technique to examine gate oxide anomaly and particulate within oxide interface for MOS devices whilst preserving the silicon substrate is presented in this paper. This technique incorporates parallel face lapping and a highly selective polysilicon chemical etch to uncover gate oxide without difficulty. Case studies of two types of MOS devices are also presented in this paper.

引用

页码：28 / 31

页数：4

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