A LINK REMOVAL METHODOLOGY FOR NETWORKS-ON-CHIP ON RECONFIGURABLE SYSTEMS

被引：0

作者：

Wang, Daihan ^{[1
]}

Matsutani, Hiroki ^{[1
]}

Amano, Hideharu ^{[1
]}

Koibuchi, Michihiro ^{[2
]}

机构：

[1] Keio Univ, Yokohama, Kanagawa 223, Japan

[2] Natl Inst Informat, Tokyo, Japan

来源：

2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2 | 2008年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

While the regular 2-D mesh topology has been utilized for most of Net-work-on-Chips (NoCs) on FPGAs, spatially biased traffic in some applications make some customization method feasible. A link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost with enough performance being kept. Two policies are proposed to avoid deadlocks and better performance can be achieved compared with up*/down* routing on the irregular topology with links removed. In the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.

引用

页码：269 / +

页数：2

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