Variability and Sensitivity to Process Parameters Variations in InGaAs Dual-Gate Ultra-Thin Body MOSFETs: A Scaling Perspective

被引:0
|
作者
Zagni, Nicolo [1 ]
Puglisi, Francesco Maria [1 ]
Verzellesi, Giovanni [2 ]
Pavan, Paolo [1 ]
机构
[1] Univ Modena & Reggio Emilia, DIEF, Via P Vivarelli 10-1, I-41125 Modena, MO, Italy
[2] Univ Modena & Reggio Emilia, DISMI, Via Amendola 2, I-42122 Reggio Emilia, RE, Italy
关键词
Variability; InGaAs; Dual-Gate Ultra-Thin Body; Sensitivity; Scaled Devices;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, we present a combined analysis on the statistical variability of threshold voltage, on-state current, and leakage current of III-V ultra-scaled MOSFETs. In addition, we analyze the sensitivity of threshold voltage to critical geometrical and process parameters variations (i.e., gate length, channel thickness, oxide thickness and channel doping). Our analysis verifies the scaling potential of the InGaAs technology from the variability/sensitivity standpoint for two technological nodes (L-G = 15 nm, L-G = 10.4 nm), by means of Quantum Drift-Diffusion (QDD) simulations. The structure under investigation is a template Dual-Gate Ultra-Thin Body device realized following ITRS projections. The variability sources under consideration are: Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate- Line Edge Roughness (LER). The sensitivity analysis of threshold voltage is performed by considering also the effects of statistical variability to evaluate their combined effect. The results of the statistical variability analysis highlight the importance of carefully controlling Body-LER, as forecasted in the new IRDS report. Moreover, the combined effect of variability and sensitivity to channel thickness are found to be critical to the scaling process (down to L-G = 10.4 nm), as it leads to significant leakage increase or performance reduction, potentially resulting in always-on devices.
引用
收藏
页数:5
相关论文
共 31 条
  • [21] Performance Enhancement of Capacitive-Coupling Dual-gate Ion-Sensitive Field-Effect Transistor in Ultra-Thin-Body
    Jang, Hyun-June
    Cho, Won-Ju
    SCIENTIFIC REPORTS, 2014, 4
  • [22] Electrical Properties of Ultra-Thin Body (111) Ge-On-Insulator n-Channel MOSFETs Fabricated by Smart-Cut Process
    Lim, Cheol-Min
    Zhao, Ziqiang
    Sumita, Kei
    Toprasertpong, Kasidit
    Takenaka, Mitsuru
    Takagi, Shinichi
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2021, 9 : 612 - 617
  • [23] Ultra-Thin-Body Self-Aligned InGaAs MOSFETs on Insulator (III-V-O-I) by a Tight-Pitch Process
    Lin, Jianqiang
    Czomomaz, Lukas
    Daix, Nicolas
    Antoniadis, Dimitri A.
    del Alamo, Jesus A.
    2014 72ND ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2014, : 217 - +
  • [24] A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation
    Lime, F.
    Ritzenthaler, R.
    Ricoma, M.
    Martinez, F.
    Pascal, F.
    Miranda, E.
    Faynot, O.
    Iniguez, B.
    SOLID-STATE ELECTRONICS, 2011, 57 (01) : 61 - 66
  • [25] Suppression of stand-by tunnel current in ultra-thin gate oxide MOSFETs by dual oxide thickness-multiple threshold voltage CMOS (DOT-MTCMOS)
    Inukai, Takashi
    Hiramoto, Toshiro
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2000, 39 (5 B): : 2287 - 2290
  • [26] Suppression of stand-by tunnel current in ultra-thin gate oxide MOSFETs by dual oxide thickness-multiple threshold voltage CMOS (DOT-MTCMOS)
    Inukai, T
    Hiramoto, T
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2000, 39 (4B): : 2287 - 2290
  • [27] Base oxide scaling limit of thermally-enhanced remote plasma nitridation (TE-RPN) process for ultra-thin gate dielectric formation
    Yu, MC
    Huang, HT
    Chen, CH
    Wang, MF
    Hou, TH
    Lin, YM
    Jans, SM
    Diaz, CH
    Sun, J
    Fang, YK
    Chen, SC
    Yu, CH
    Liang, MS
    2001 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS, 2001, : 179 - 182
  • [28] Mobility enhancement in uniaxially strained (110) oriented ultra-thin body single- and double-gate MOSFETs with SOI thickness of less than 4 nm
    Shimizu, Ken
    Hiramoto, Toshiro
    2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 715 - +
  • [29] A strategy using a copper/low-k BEOL process to prevent negative-bias temperature instability (NBTI) in p-MOSFETs with ultra-thin gate oxide
    Suzuki, A
    Tabuchi, K
    Kimura, H
    Hasegawa, T
    Kadomura, S
    Kakamu, K
    Kudo, H
    Kawano, M
    Tsukune, A
    Yamada, M
    2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, : 216 - 217
  • [30] Electrostatics Improvement in 3-D Tri-gate Over Ultra-Thin Body Planar InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Scaled Gate-to-Drain/Gate-to-Source Separation
    Radosavljevic, M.
    Dewey, G.
    Basu, D.
    Boardman, J.
    Chu-Kung, B.
    Fastenau, J. M.
    Kabehie, S.
    Kavalieros, J.
    Le, V.
    Liu, W. K.
    Lubyshev, D.
    Metz, M.
    Millard, K.
    Mukherjee, N.
    Pan, L.
    Pillarisetty, R.
    Rachmady, W.
    Shah, U.
    Then, H. W.
    Chau, Robert
    2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,