A strategy using a copper/low-k BEOL process to prevent negative-bias temperature instability (NBTI) in p-MOSFETs with ultra-thin gate oxide

被引：11

作者：

Suzuki, A ^{[1
]}

Tabuchi, K ^{[1
]}

Kimura, H ^{[1
]}

Hasegawa, T ^{[1
]}

Kadomura, S ^{[1
]}

Kakamu, K ^{[1
]}

Kudo, H ^{[1
]}

Kawano, M ^{[1
]}

Tsukune, A ^{[1
]}

Yamada, M ^{[1
]}

机构：

[1] Sony Corp, SNC, LSI Technol Dev Grp, Atsugi, Kanagawa 2430014, Japan

来源：

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIT.2002.1015458

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper is a report on the effect of processing to form interconnects by using copper and a material with a low dielectric constant (copper/low-k) on the negative-bias temperature instability (NBTI) of p-MOSFETs. We found that the NBT-stress lifetime of copper/low-k interconnects is shorter than that of aluminum/SiO2, interconnects. The NBTI strongly depends on the cap layer over the copper/low-k layer, on the intermetal dielectric (IMD) film, on the barrier-metal film, and on the temperature of post-metal annealing (PMA). Based on these results, we developed methods for reducing the NBTI in next-generation MOSFETs.

引用

页码：216 / 217

页数：2

共 12 条

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