Internal feedback bridging faults in combinational CMOS circuits: Analysis and testing

被引：0

作者：

Miura, Y ^{[1
]}

Seno, S ^{[1
]}

机构：

[1] Tokyo Metropolitan Univ, Grad Sch Engn, Tokyo, Japan

来源：

ETW 2001: IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we analyze fault behaviors of internal feedback bridging faults by using a simple circuit model consisting of 2-input NAND gate and NOT gate. From analysis results we find that they are more complex than those associated with external feedback bridging faults. We expose that they cause internal oscillation and IDDQ-only failure as well as latch and oscillation behavior. We also discuss methods for detecting this kind of fault.

引用

页码：9 / 16

页数：8

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