Internal feedback bridging faults in combinational CMOS circuits: Analysis and testing

被引：0

作者：

Miura, Y ^{[1
]}

Seno, S ^{[1
]}

机构：

[1] Tokyo Metropolitan Univ, Grad Sch Engn, Tokyo, Japan

来源：

ETW 2001: IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we analyze fault behaviors of internal feedback bridging faults by using a simple circuit model consisting of 2-input NAND gate and NOT gate. From analysis results we find that they are more complex than those associated with external feedback bridging faults. We expose that they cause internal oscillation and IDDQ-only failure as well as latch and oscillation behavior. We also discuss methods for detecting this kind of fault.

引用

页码：9 / 16

页数：8

共 50 条

[31] TESTING FOR STUCK-AT-FAULTS IN CMOS CIRCUITS
ISMAEEL, AA
NAJEM, Z
INTERNATIONAL JOURNAL OF ELECTRONICS, 1987, 63 (05) : 677 - 685
[32] A SINGLE BRIDGING FAULT LOCATION TECHNIQUE FOR CMOS COMBINATIONAL-CIRCUITS
YAMAZAKI, K
YAMADA, T
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1995, E78D (07) : 817 - 821
[33] Testing CMOS combinational iterative logic arrays for realistic faults
Gizopoulos, D
Nikolos, D
Paschalis, A
INTEGRATION-THE VLSI JOURNAL, 1996, 21 (03) : 209 - 228
[34] TESTING MULTIPLE-OUTPUT CMOS COMBINATIONAL-CIRCUITS
ISMAEEL, AA
INTERNATIONAL JOURNAL OF ELECTRONICS, 1989, 67 (04) : 513 - 521
[35] Statistical analysis of multiple intermittent faults in combinational circuits
AbdElBarr, MH
Ansari, SI
INTERNATIONAL JOURNAL OF ELECTRONICS, 1996, 80 (05) : 647 - 660
[36] Analysis of fault detection probability of CMOS combinational circuits and its application to signature testing
Iwasaki, Kazuhiko, 1600, (21):
[37] DETECTING I/O AND INTERNAL FEEDBACK BRIDGING FAULTS
XU, SY
SU, SYH
IEEE TRANSACTIONS ON COMPUTERS, 1985, 34 (06) : 553 - 557
[38] Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
Lee, T
Hajj, IN
Rudnick, EM
Patel, JH
14TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1996, : 456 - 462
[39] Impact of technology scaling on bridging fault detections in sequential and combinational CMOS circuits
Semenov, O
Sachdev, M
2000 IEEE INTERNATIONAL WORKSHOP ON DEFECT BASED TESTING, PROCEEDINGS, 2000, : 36 - 41
[40] MODEL AND RANDOM-TESTING PROPERTIES OF INTERMITTENT FAULTS IN COMBINATIONAL CIRCUITS
SAVIR, J
JOURNAL OF DESIGN AUTOMATION & FAULT-TOLERANT COMPUTING, 1978, 2 (03): : 215 - 230

← 1 2 3 4 5 →