共 50 条
- [21] Reversible priority encoder design and implementation using quantum-dot cellular automata IET QUANTUM COMMUNICATION, 2020, 1 (02): : 72 - 78
- [23] Design and Performance Analysis for the Reversible Realization of Adder/Subtractor Circuit 2017 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN COMPUTING AND COMMUNICATION TECHNOLOGIES (ICETCCT), 2017, : 162 - 167
- [24] Analysis and Design of Reversible Excess-3 Adder and Subtractor 2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2016, : 397 - 400
- [26] Monoimmittance priority encoder PHOTONICS APPLICATIONS IN ASTRONOMY, COMMUNICATIONS, INDUSTRY, AND HIGH-ENERGY PHYSICS EXPERIMENTS 2018, 2018, 10808
- [27] Reversible Adder/Subtractor with Overflow Detector 2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
- [30] Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing 2015 IEEE 45TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, 2015, : 36 - 41