High speed bit-serial parallel processing on array architecture

被引：0
|
作者：
Ito, K
Shimizugashira, T
Kunieda, H
机构：
来源：
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997 | 1996年
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D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Word-parallel bit-serial processing is a solution to high speed processing suitable for VLSI, In this paper a new bit-serial parallel processing architecture is proposed, A VLSI chip for a digital filter is designed based on the proposed architecture and it is implemented on a gate array chip. Through the implementation, it Is verified that bit-serial parallel processing on an array architecture achieves high speed processing and easy design.
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页码：667 / 668
页数：2
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