A New Bit-Serial Architecture of Rank-Order Filter

被引：2

作者：

Yamamoto, Takuya ^{[1
]}

Moshnyaga, Vasily G. ^{[1
]}

机构：

[1] Fukuoka Univ, Dept Elect Engn & Comp Sci, Jonan Ku, Fukuoka 8140180, Japan

来源：

2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2009年

关键词：

LEVEL SYSTOLIC ARRAY;

D O I：

10.1109/MWSCAS.2009.5236042

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a new architecture of rank-order median filter. The architecture processes all window samples in parallel in the bit-serial manner. Unlike related architectures, it neither sorts/swaps nor modifies the window samples and requires less hardware resources. To process k samples, each of N-bits in size, the architecture uses N shift registers of k bits each and a simple logic. It produces the result in N+1 clock cycles independently to the window size.

引用

页码：511 / 514

页数：4

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