A CMOS Under-voltage Lockout Circuit

被引：0
|
作者：
Hoque, Mohammad R. [1 ]
Ang, Simon S. [2 ]
机构：
[1] Texas Instruments Inc, Portable Power Management Grp, Dallas, TX 75002 USA
[2] Univ Arkansas, Dept Elect Engn, Bell Engn Ctr 3217, Fayetteville, AR 72701 USA
来源：
WCECS 2008: WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE | 2008年
关键词：
power good monitor; voltage protection circuit; UVLO;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
Anew configuration for a CMOS under voltage lockout (UVLO) circuit is described. This circuit consists of a pre-regulator, a hysteresis control resistor divider and an inverter pair. The UVLO circuit was fabricated using a 0.5 mu m CMOS technology operating at a supply voltage of up to 5V, yielding a low quiescent current of 12 mu A, an input high threshold voltage of 3.75 V and a hysteresis of 0.55 V.
引用
收藏
页码：173 / 176
页数：4
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