On-chip learning for a scalable hybrid neural architecture

被引：0
|
作者：
Alhalabi, BA
Bayoumi, MA
机构：
来源：
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | 1997年
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D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A new class of neural architecture with on-chip learning has been developed. Learning has been implemented in analog while the control is performed in digital. An efficient analog technique has been developed to refresh the capacitors that store the synaptic weights. The graded update signals are also generated in analog, it is added to the weights via simple local analog adders. This localization of weight update makes the complexity of the learning procedure independent of the overall network size. The new architecture is based on a computational kernel composed of two chips; the SynChip and NeuChip. The SynChip consists of an array of 32x32 analog synapse modules (SynMod), a digital control block (SynLogic), a voltage reference of 16 levels, and 32 refreshing blocks (RefMod). The NeuChip consists of a 32 analog neurons modules (NeuMod) and a digital control block (NeuLogic). This two-chip set can be cascaded on a regular grid to build large size neural networks.
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页码：677 / 680
页数：4
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