On-chip learning for a scalable hybrid neural architecture

被引：0
|
作者：
Alhalabi, BA
Bayoumi, MA
机构：
来源：
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | 1997年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A new class of neural architecture with on-chip learning has been developed. Learning has been implemented in analog while the control is performed in digital. An efficient analog technique has been developed to refresh the capacitors that store the synaptic weights. The graded update signals are also generated in analog, it is added to the weights via simple local analog adders. This localization of weight update makes the complexity of the learning procedure independent of the overall network size. The new architecture is based on a computational kernel composed of two chips; the SynChip and NeuChip. The SynChip consists of an array of 32x32 analog synapse modules (SynMod), a digital control block (SynLogic), a voltage reference of 16 levels, and 32 refreshing blocks (RefMod). The NeuChip consists of a 32 analog neurons modules (NeuMod) and a digital control block (NeuLogic). This two-chip set can be cascaded on a regular grid to build large size neural networks.
引用
收藏
页码：677 / 680
页数：4
相关论文
共 50 条
  • [41] An isometric on-chip multiprocessor architecture
    Ogoubi, Etienne
    Hafid, Abdel Hakim
    Turcotte, Marcel
    2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 991 - +
  • [42] Memory Organization and Structures for On-Chip Learning in Spiking Neural Networks
    Schaefer, Clemens J. S.
    Joshi, Siddharth
    2020 IEEE 63RD INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2020, : 599 - 602
  • [43] On-Chip Unsupervised Learning Using STDP in a Spiking Neural Network
    Gupta, Abhinav
    Saurabh, Sneh
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2023, 22 : 365 - 376
  • [44] Biologically-inspired on-chip learning in pulsed neural networks
    Lehmann, T
    Woodburn, R
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1999, 18 (2-3) : 117 - 131
  • [45] Ultrahigh Density Memristor Neural Crossbar for On-Chip Supervised Learning
    Chabi, Djaafar
    Wang, Zhaohao
    Bennett, Christopher
    Klein, Jacques-Olivier
    Zhao, Weisheng
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2015, 14 (06) : 954 - 962
  • [46] A general-purpose neural network with on-chip BP learning
    Lu, C
    Shi, BX
    Chen, L
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS, 2002, : 520 - 523
  • [47] A mixed-signal VLSI neural network with on-chip learning
    Mirhassani, M
    Ahmadi, M
    Miller, WC
    CCECE 2003: CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-3, PROCEEDINGS: TOWARD A CARING AND HUMANE TECHNOLOGY, 2003, : 591 - 594
  • [48] Design and electrical simulation of on-chip neural learning based on nanocomponents
    He, M.
    Klein, J. -O.
    Belhaire, E.
    ELECTRONICS LETTERS, 2008, 44 (09) : 575 - +
  • [49] Biologically-Inspired On-Chip Learning in Pulsed Neural Networks
    Torsten Lehmann
    Robin Woodburn
    Analog Integrated Circuits and Signal Processing, 1999, 18 : 117 - 131
  • [50] Digital Implementation of On-Chip Hebbian Learning for Oscillatory Neural Network
    Luhulima, Edgar
    Abernot, Madeleine
    Corradi, Federico
    Todri-Sanial, Aida
    2023 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, ISLPED, 2023,
12345