Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology

被引：0

作者：

Tsugawa, H. ^{[1
]}

Takahashi, H. ^{[1
]}

Nakamura, R. ^{[1
]}

Umebayashi, T. ^{[1
]}

Ogita, T. ^{[1
]}

Okano, H. ^{[1
]}

Iwase, K. ^{[1
]}

Kawashima, H. ^{[1
]}

Yamasaki, T. ^{[2
]}

Yoneyama, D. ^{[2
]}

Hashizume, J. ^{[1
]}

Nakajima, T. ^{[1
]}

Murata, K. ^{[1
]}

Kanaishi, Y. ^{[1
]}

Ikeda, K. ^{[2
]}

Tatani, K. ^{[1
]}

Nagano, T. ^{[1
]}

Nakayama, H. ^{[2
]}

Haruta, T. ^{[1
]}

Nomoto, T. ^{[1
]}

机构：

[1] Sony Semicond Solut Corp, Atsugi, Kanagawa, Japan

[2] Sony Semicond Mfg Corp, Nagasaki, Japan

来源：

2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We developed a CMOS image sensor (CIS) chip, which is stacked pixel/DRAM/logic. In this CIS chip, three Si substrates are bonded together, and each substrate is electrically connected by two-stacked through-silica vias (TSVs) through the CIS or dynamic random access memory (DRAM). We obtained low resistance, low leakage current, and high reliability characteristics of these TSVs. Connecting metal with TSVs through DRAM can be used as low resistance wiring for a power supply. The Si substrate of the DRAM can be thinned to 3 mu m, and its memory retention and operation characteristics are sufficient for specifications after thinning. With this stacked CIS chip, it is possible to achieve less rolling shutter distortion and produce super slow motion video.

引用

页数：4

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