Design and Verification for Data Acquisition Interface ADC_USB IP Core

被引：0

作者：

Ling, Bo ^{[1
]}

Li, Zheying ^{[2
]}

Zhang, Shaozhen ^{[1
]}

机构：

[1] Beijing Jiaotong Univ, Sch Elect & Informat Engn, Beijing 100044, Peoples R China

[2] Beijing Union Univ, Coll Informat, Beijing 100101, Peoples R China

来源：

2012 INTERNATIONAL WORKSHOP ON INFORMATION AND ELECTRONICS ENGINEERING | 2012年 / 29卷

基金：

中国国家自然科学基金;

关键词：

USB; ADC; Verilog HDL; IP core;

D O I：

10.1016/j.proeng.2012.01.026

中图分类号：

TH [机械、仪表工业];

学科分类号：

0802 ;

摘要：

A series of portable mass storage devices are arising due to the effective support from USB interface for its special features, such as easy to use, high-speed and low power. ADC_USB IP core is to achieve data acquisition and efficient data transfer to PC. The USB bus protocol and communication principle is introduced firstly. Then the design and verification of ADC_USB IP core are discussed in detail. In addition, data streams and transport are analyzed in detail. Modules of ADC_USB protocol controller are designed with Verilog HDL. The design is synthesized with Quartus tool and verified by FPGA. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of Harbin University of Science and Technology

引用

页码：699 / 704

页数：6

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