Substrate bias effect on cycling induced performance degradation of flash EEPROMs

Cycling induced performance degradation of flash EEPROMs has been reported for V-B=0 and V-B<0 programming operation. Compared to V-B=0, V-B<0 programming shows lower interface degradation for identical cumulative charge fluence (for program) during repetitive program/erase cycling. Reduction in programming gate current has been found to be lower for V-B<0 operation under identical interface damage as the V-B=0 case. As a consequence, programming under V-B<0 condition has been found to cause lower degradation of programming time and programmed V-T due to cycling.