Substrate bias effect on cycling induced performance degradation of flash EEPROMs

被引：0
|
作者：
Mahapatra, S [1 ]
Shukuri, S [1 ]
Bude, J [1 ]
机构：
[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India
来源：
16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/ICVD.2003.1183140
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
Cycling induced performance degradation of flash EEPROMs has been reported for V-B=0 and V-B<0 programming operation. Compared to V-B=0, V-B<0 programming shows lower interface degradation for identical cumulative charge fluence (for program) during repetitive program/erase cycling. Reduction in programming gate current has been found to be lower for V-B<0 operation under identical interface damage as the V-B=0 case. As a consequence, programming under V-B<0 condition has been found to cause lower degradation of programming time and programmed V-T due to cycling.
引用
收藏
页码：223 / 226
页数：4
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