Dual-bit/cell SONOS flash EEPROMs: Impact of channel engineering on programming speed and bit coupling effect

被引：9
|
作者：
Datta, A. [1 ]
Kumar, P. Bharath [1 ]
Mahapatra, S. [1 ]
机构：
[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India
来源：
IEEE ELECTRON DEVICE LETTERS | 2007年 / 28卷 / 05期
关键词：
bit coupling; compensation implant; flash; halo implant; localized charge storage; non volatile semiconductor memory (NVSM); program speed; read disturb; SONOS; 2-bit operation;
D O I：
10.1109/LED.2007.895406
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Programming performance of dual-bit silicon-oxide-nitride-oxide-silicon memories is studied on cells fabricated using different channel engineering schemes. Both halo and compensation implants are shown to impact the programming speed, bit coupling, and read disturb, and can be suitably adjusted to optimize the cell operation. The doping dependence of bit coupling and the programming speed are verified using well-calibrated 2-D device simulations.
引用
收藏
页码：446 / 448
页数：3
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