Substrate bias effect on cycling induced performance degradation of flash EEPROMs

被引：0
|
作者：
Mahapatra, S [1 ]
Shukuri, S [1 ]
Bude, J [1 ]
机构：
[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India
来源：
16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/ICVD.2003.1183140
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
Cycling induced performance degradation of flash EEPROMs has been reported for V-B=0 and V-B<0 programming operation. Compared to V-B=0, V-B<0 programming shows lower interface degradation for identical cumulative charge fluence (for program) during repetitive program/erase cycling. Reduction in programming gate current has been found to be lower for V-B<0 operation under identical interface damage as the V-B=0 case. As a consequence, programming under V-B<0 condition has been found to cause lower degradation of programming time and programmed V-T due to cycling.
引用
收藏
页码：223 / 226
页数：4
相关论文
共 50 条
  • [1] Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operation
    Nair, DR
    Mohapatra, NR
    Mahapatra, S
    Shukuri, S
    Bude, JD
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (01) : 32 - 37
  • [2] A CONVERGENCE SCHEME FOR OVER-ERASED FLASH EEPROMS USING SUBSTRATE-BIAS-ENHANCED HOT-ELECTRON INJECTION
    HU, CY
    KENCKE, DL
    BANERJEE, SK
    RICHART, R
    BANDYOPADHYAY, B
    MOORE, B
    IBOK, E
    GARG, S
    IEEE ELECTRON DEVICE LETTERS, 1995, 16 (11) : 500 - 502
  • [3] Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory
    Zhao, Wei
    He, Yue-Song
    Huang, Chunchieh
    Mei, Len
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2010, 49 (07) : 0741051 - 0741054
  • [4] Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs
    Mohapatra, NR
    Mahapatra, S
    Rao, VR
    Shukuri, S
    Bude, J
    41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2003, : 518 - 522
  • [5] The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs
    Mohapatra, NR
    Nair, DR
    Mahapatra, S
    Rao, VR
    Shukuri, S
    ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, : 541 - 544
  • [6] Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory
    Huang, KC
    Fang, YK
    Yaung, DN
    Chen, CW
    Sung, HC
    Kuo, DS
    Wang, CS
    Liang, MS
    IEEE ELECTRON DEVICE LETTERS, 1999, 20 (08) : 412 - 414
  • [7] Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory
    VLSI Technology Laboratory, Department of Electrical Engineering, Natl. Cheng Kung University, Tainan, Taiwan
    不详
    不详
    IEEE Electron Device Lett, 8 (412-414):
  • [8] Analyzing the performance degradation of flash A/D converters due to substrate noise coupling
    Stefanou, Athanasios
    Gielen, Georges
    2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3, 2007, : 360 - 363
  • [9] Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation
    Nair, DR
    Mahapatra, S
    Shukuri, S
    Bude, JD
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (04) : 534 - 540
  • [10] Low voltage flash memory by use of a substrate bias
    Mastrapasqua, M
    MICROELECTRONIC ENGINEERING, 1999, 48 (1-4) : 389 - 394
12345