A CONVERGENCE SCHEME FOR OVER-ERASED FLASH EEPROMS USING SUBSTRATE-BIAS-ENHANCED HOT-ELECTRON INJECTION

被引：12

作者：

HU, CY ^{[1
]}

KENCKE, DL ^{[1
]}

BANERJEE, SK ^{[1
]}

RICHART, R ^{[1
]}

BANDYOPADHYAY, B ^{[1
]}

MOORE, B ^{[1
]}

IBOK, E ^{[1
]}

GARG, S ^{[1
]}

机构：

[1] ADV MICRO DEVICES INC,AUSTIN,TX 78741

来源：

IEEE ELECTRON DEVICE LETTERS | 1995年 / 16卷 / 11期

关键词：

D O I：

10.1109/55.468280

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate Flash EEPROM's, By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown to be more than a hundred times shorter than the previous scheme, With the convergence operation performed near the ON-OFF transition region of the cells, the total drain current for all the converged cells is reduced and low power consumption is achieved.

引用

页码：500 / 502

页数：3

共 12 条

[1] Convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection
Hu, C.-Y.
Kencke, D.L.
Banerjee, S.K.
Richart, R.
Bandyopadhyay, B.
Moore, B.
Ibok, E.
Garg, S.
1600, IEEE, Piscataway, NJ, United States (16):
[2] Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current
Sonoda, K
Tanizawa, M
Shimizu, S
Araki, Y
Kawai, S
Ogura, T
Kobayashi, S
Ishikawa, K
Eimori, T
Inoue, Y
Ohji, Y
Kotani, N
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (10) : 1726 - 1730
[3] Compact modeling of flash memory cells including substrate-bias-dependent hot-electron gate current
Sonoda, K
Tanizawa, M
Shimizu, S
Araki, Y
Kawai, S
Ogura, T
Kobayashi, S
Ishikawa, K
Inoue, Y
Kotani, N
2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2003, : 215 - 218
[4] P-WELL BIAS DEPENDENCE OF ELECTRON TRAPPING IN GATE OXIDE OF N-MOSFETS DURING SUBSTRATE HOT-ELECTRON INJECTION
ZHAO, SP
TAYLOR, S
ECCLESTON, W
BARLOW, KJ
ELECTRONICS LETTERS, 1992, 28 (22) : 2080 - 2082
[5] Forward bias enhanced channel hot electron injection for low-level programming improvement in multilevel flash memory
Cho, CYS
Chen, MJ
IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (07) : 1204 - 1207
[6] Enhanced band-to-band-tunneling-induced hot-electron injection in p-channel flash by band-gap offset modification
Wang, Chi-Chao
Chang-Liao, Kuei-Shu
Lu, Chun-Yuan
Wang, Tien-Ko
IEEE ELECTRON DEVICE LETTERS, 2006, 27 (09) : 749 - 751
[7] Degradation of flash memory using drain-avalanche hot electron (DAHE) self-convergence operation scheme
Shen, SJ
Yang, ECS
Wong, WJ
Wang, YS
Lin, CJ
Liang, MS
Hsu, CCH
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS, 1998, 37 (7A): : L778 - L780
[8] Substrate-Bias Assisted Hot Electron Injection Method for High-Speed, Low-Voltage, and Multi-Bit Flash Memories
An, Ho-Myoung
Kim, Hee-Dong
Zhang, Yongjie
Seo, Yu Jeong
Kim, Tae Geun
JAPANESE JOURNAL OF APPLIED PHYSICS, 2011, 50 (12)
[9] A Four-Bit-Per-Cell Program Method with Substrate-Bias Assisted Hot Electron Injection for Charge Trap Flash Memory Devices
An, Ho-Myoung
Kim, Hee-Dong
Kim, Byungcheul
Kim, Tae Geun
JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2013, 13 (05) : 3293 - 3297
[10] Substrate-bias assisted hot electron injection method for high-speed, low-voltage, and multi-bit flash memories
School of Electrical Engineering, Korea University, Seoul 136-713, Korea, Republic of
Jpn. J. Appl. Phys., 12

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