Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors

被引:17
|
作者
Radojkovic, Petar [1 ,2 ]
Cakarevic, Vladimir [1 ,2 ]
Verdu, Javier [2 ]
Pajuelo, Alex [2 ]
Cazorla, Francisco J. [1 ,3 ]
Nemirovsky, Mario [4 ]
Valero, Mateo [1 ,2 ]
机构
[1] Barcelona Supercomp Ctr, Barcelona 08034, Spain
[2] Univ Politecn Cataluna, ES-08034 Barcelona, Spain
[3] Spanish Natl Res Council IIIA CSIC, Barcelona 08034, Spain
[4] ICREA Res Barcelona Supercomp Ctr, Barcelona 08034, Spain
关键词
Chip multithreading (CMT); process scheduling; performance modeling; SMT PROCESSORS; PERFORMANCE;
D O I
10.1109/TPDS.2012.311
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The introduction of multithreaded processors comprised of a large number of cores with many shared resources makes thread scheduling, and in particular optimal assignment of running threads to processor hardware contexts to become one of the most promising ways to improve the system performance. However, finding optimal thread assignments for workloads running in state-of-the-art multicore/multithreaded processors is an NP-complete problem. In this paper, we propose BlackBox scheduler, a systematic method for thread assignment of multithreaded network applications running on multicore/multithreaded processors. The method requires minimum information about the target processor architecture and no data about the hardware requirements of the applications under study. The proposed method is evaluated with an industrial case study for a set of multithreaded network applications running on the UltraSPARC T2 processor. In most of the experiments, the proposed thread assignment method detected the best actual thread assignment in the evaluation sample. The method improved the system performance from 5 to 48 percent with respect to load balancing algorithms used in state-of-the-art OSs, and up to 60 percent with respect to a naive thread assignment.
引用
收藏
页码:2513 / 2525
页数:13
相关论文
共 50 条
  • [31] Multithreaded extension to multicluster VLIW processors for embedded applications
    Barretta, D
    Fornaciari, W
    Sami, M
    Bagni, D
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 748 - 749
  • [32] PERFORMANCE TRADEOFFS IN MULTITHREADED PROCESSORS
    AGARWAL, A
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 1992, 3 (05) : 525 - 539
  • [33] A clustered approach to multithreaded processors
    Krishnan, V
    Torrellas, J
    FIRST MERGED INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM & SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING, 1998, : 627 - 634
  • [34] Implicitly-multithreaded processors
    Park, I
    Falsafi, B
    Vijaykumar, TN
    30TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS, 2003, : 39 - 50
  • [35] RPPM: Rapid Performance Prediction of Multithreaded Applications on Multicore Hardware
    De Pestel, Sander
    Van den Steen, Sam
    Akram, Shoaib
    Eeckhout, Lieven
    IEEE COMPUTER ARCHITECTURE LETTERS, 2018, 17 (02) : 183 - 186
  • [36] Clustered speculative multithreaded processors
    Marcuello, Pedro
    Gonzalez, Antonio
    Proceedings of the International Conference on Supercomputing, 1999, : 365 - 372
  • [37] Loop scheduling for multithreaded processors
    Dimitriou, G
    Polychronopoulos, C
    INTERNATIONAL CONFERENCE ON PARALLEL COMPUTING IN ELECTRICAL ENGINEERING, 2004, : 361 - 366
  • [38] Time-predictable Execution of Multithreaded Applications on Multicore Systems
    Alhammad, Ahmed
    Pellizzoni, Rodolfo
    2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE), 2014,
  • [39] A multithreaded communication engine for multicore architectures
    Trahay, Francois
    Brunet, Elisabeth
    Denis, Alexandre
    Namyst, Raymond
    2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8, 2008, : 190 - 196
  • [40] Thread-Aware Adaptive Prefetcher on Multicore Systems: Improving the Performance for Multithreaded Workloads
    Liu, Peng
    Yu, Jiyang
    Huang, Michael C.
    ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2016, 13 (01)