An advanced low power, high performance, strained channel 65nm technology

被引：0

作者：

Tyagi, S ^{[1
]}

Auth, C ^{[1
]}

Bai, P ^{[1
]}

Curello, G ^{[1
]}

Deshpande, H ^{[1
]}

Gannavaram, S ^{[1
]}

Golonzka, O ^{[1
]}

Heussner, R ^{[1
]}

James, R ^{[1
]}

Kenyon, C ^{[1
]}

Lee, SH ^{[1
]}

Lindert, N ^{[1
]}

Liu, M ^{[1
]}

Nagisetty, R ^{[1
]}

Natarajan, S ^{[1
]}

Parker, C ^{[1
]}

Sebastian, J ^{[1
]}

Sell, B ^{[1
]}

Sivakumar, S ^{[1
]}

St Amour, A ^{[1
]}

Tone, K ^{[1
]}

机构：

[1] Intel Corp, Portland Technol Dev, Hillsboro, OR 97124 USA

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/um, transistors have record currents of 1.21mA/um and 0.71mA/um for NMOS and PMOS respectively. This industry leading 65nm technology is currently in high volume manufacturing.

引用

页码：1070 / 1072

页数：3

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