Development of Exposed Die Large Body to Die Size Ratio Wafer Level Package Technology

被引:0
|
作者
Osenbach, J. [1 ]
Emerich, S. [1 ]
Golick, L. [1 ]
Cate, S. [2 ]
Chan, M. [3 ]
Yoon, S. W. [3 ]
Lin, Y. J. [4 ]
Wong, K. [5 ]
机构
[1] LSI Corp USA, Allentown, PA 18109 USA
[2] LSI Corp USA, San Jose, CA 95131 USA
[3] STATSChipPAC Ltd, Singapore 768442, Singapore
[4] STATSChipPAC Ltd, Singapore 738068, Singapore
[5] STATSChipPAC Inc, Fremont, CA 94538 USA
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Traditionally fan out wafer level package technology has been associated with lower power, smaller body sizes (typically < 8mmx8mm), small body-to-die size area ratios (< 2) and fine pitch BGAs (0.4mm or less). This work extends this technology to larger body sizes up to 13mm x 13mm, higher powers, > 5W, and larger body-to-die size area ratios up to 10.5. It is shown that such packages can be readily manufactured in a 300mm wafer format with yields exceeding 99% and final package warpage < 75um. Further, data is presented showing that 10mm x 10mm packages with a body to die area ratio of 6.25 are compatible with moisture sensitivity level 1, and easily pass 2000 temperature cycle (-55C to 125C air to air) and 288 hr uHAST. That is to say they have reliability that is compatible with that required for all storage and communications applications. Larger package sizes, up to 13mm x 13mm, and body-to-die area ratios, > 10, have also been demonstrated. However, failures in extended temperature cycle were found in these larger packages. All of the failures were due to pre-identified package design flaws that violated well established rules. This indicates if such packages were designed with no rule violations then they would meet the reliability requirements needed for communications and storage applications.
引用
收藏
页码:952 / 955
页数:4
相关论文
共 50 条
  • [41] Development of Package-on-Package Using Embedded Wafer-Level Package Approach
    Chong, Ser Choong
    Wee, David Ho Soon
    Rao, Vempati Srinivasa
    Vasarla, Nagendra Sekhar
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (10): : 1654 - 1662
  • [42] Development of subtractive wafer level chip scale package
    不详
    [J]. NEC RESEARCH & DEVELOPMENT, 2001, 42 (02): : 251 - 251
  • [43] Cost Effective Wafer Level Chip Size Package Technology and Application to the Next Generation Automotive Radar
    Tsukashima, K.
    Kubota, M.
    Baba, O.
    Tango, H.
    Yonamine, A.
    Tokumitsu, T.
    Hasegawa, Y.
    [J]. 40TH EUROPEAN MICROWAVE CONFERENCE, 2010, : 280 - 283
  • [44] ULTRA WAFER THINNING AND DICING TECHNOLOGY FOR STACKED DIE PACKAGES
    Zhang, Renfu
    Liu, Hao
    Li, Bo
    Sugiya, Tetsukazu
    [J]. 2016 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2016,
  • [45] Thermal Performance Of FCMBGA: Exposed Molded Die Compared To Lidded Package
    Galloway, Jesse
    Kanuparthi, Sasanka
    Wan, Qun
    [J]. 2011 27TH ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM (SEMI-THERM), 2011, : 181 - 186
  • [46] Assembly cost reduction with wafer level die attach film
    Dunlap, Stewart
    [J]. IPACK 2007: PROCEEDINGS OF THE ASME INTERPACK CONFERENCE 2007, VOL 1, 2007, : 7 - 9
  • [47] Embedded Wafer Level BGA (eWLB) - Multi-Die
    Anandan, Ramasamy
    Jin, Yonggang
    Huang, Yaohuang
    Gan, Kah Wee
    Chua, Puay Gek
    Liu, Yun
    Geissler, Christian
    Hwa, Goh Hin
    [J]. 2010 12TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2010, : 868 - 873
  • [48] Die and wafer-level hermetic sealing for MEMS applications
    Fasoro, Abiodun A.
    Pandojirao-S, Praveen
    Popa, Dan O.
    Stephanou, Harry E.
    Agonafer, Dereje A.
    [J]. IPACK 2007: PROCEEDINGS OF THE ASME INTERPACK CONFERENCE 2007, VOL 1, 2007, : 67 - 72
  • [49] Development of Advanced Fan-out Wafer Level Package (embedded Wafer Level BGA)
    Jin, Yonggang
    Teysseyre, Jerome
    Liu, Anandan Ramasy Yun
    Goh, George
    Yoon, S. W.
    [J]. 2012 35TH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM (IEMT), 2012,
  • [50] A MEMS guide plate for a high temperature testing of a wafer level packaged die wafer
    Choi, Woo-Chang
    Ryu, Jee-Youl
    [J]. MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2011, 17 (01): : 143 - 148