Challenges and Potentials of Emerging Multicore Architectures

被引：7

作者：

Stuermer, Markus ^{[1
]}

Wellein, Gerhard ^{[2
]}

Hager, Georg ^{[2
]}

Koestler, Harald ^{[1
]}

Ruede, Ulrich ^{[1
]}

机构：

[1] Univ Erlangen Nurnberg, Lehrstuhl F Syst Simulat, Cauerstr 6, D-91058 Erlangen, Germany

[2] Regionales Rechenzentrum Erlangen, D-91058 Erlangen, Germany

来源：

HIGH PERFORMANCE COMPUTING IN SCIENCE AND ENGINEERING, GARCH/MUNICH 2007 | 2009年

关键词：

IMAGE;

D O I：

10.1007/978-3-540-69182-2_43

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present performance results on two current multicore architectures, a STI (Sony, Toshiba, and IBM) Cell processor included in the new Playstation (TM) 3 and a Sun UItraSPARC T2 ("Niagara 2") machine. On the Niagara 2 we analyze typical performance patterns that emerge from the peculiar way the memory controllers are activated on this chip using the standard STREAM benchmark and a shared-memory parallel lattice Boltzmann code. On the Cell processor we measure the memory bandwidth and run performance tests for LBM simulations. Additionally. we show results for an application in image processing on the Cell processor, where it is required to solve nonlinear anisotropic PDEs.

引用

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页码：551 / +

页数：3

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