DNW-Controllable Triggered Voltage of the Integrated Diode Triggered SCR (IDT-SCR) ESD Protection Device

被引：0
|
作者：
Lai, Da-Wei [1 ]
Tseng, Wei-Jhih [1 ]
de Raad, Gijs [1 ]
Smedes, Theo [1 ]
机构：
[1] NXP Semicond, Gerstweg 2, NL-6534 AE Nijmegen, Netherlands
来源：
2017 39TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD) | 2017年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel Integrated Diode Triggered SCR (IDT-SCR), with low capacitance (<200fF), and a controllable V-T1 is proposed for 1.8V application. The triggering is determined by the DNW biasing plus one integrated diode. The fail-current density is 16 times higher, and leakage 20 times lower, compared to a traditional capacitive-triggered bigFET.
引用
下载
收藏
页数：9
相关论文
共 50 条
  • [31] Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides
    Mergens, MPJ
    Russ, CC
    Verhaege, KG
    Armer, J
    Jozwiak, PC
    Mohn, R
    Keppens, B
    Trinh, CS
    2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 515 - 518
  • [32] Analysis of SCR Based ESD Protection Device with Optimized Low Trigger Voltage for Low Trigger Voltage Applications
    Lee, Byung-Seok
    Koo, Yong-Seo
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17 (06) : 792 - 799
  • [33] Power-Line-Triggered ESD Protection SCR for 0-20 GHz Applications in CMOS Technology
    Chang, Chun-Rong
    Lin, Chun-Yu
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 70 (12) : 6103 - 6109
  • [34] ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process
    Lin, Chun-Yu
    Chu, Li-Wei
    Ker, Ming-Dou
    Song, Ming-Hsiang
    Jou, Chewn-Pu
    Lu, Tse-Hua
    Tseng, Jen-Chou
    Tsai, Ming-Hsien
    Hsu, Tsun-Lai
    Hung, Ping-Fang
    Chang, Tzu-Heng
    2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012,
  • [35] On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
    Ker, MD
    Hsu, KC
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 529 - 532
  • [36] A Design of BJT-based ESD Protection Device combining SCR for High Voltage Power Clamps
    Jung, Jin-Woo
    Koo, Yong-Seo
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2014, 14 (03) : 339 - 344
  • [37] Design of compact-diode-SCR with low-trigger voltage for full-chip ESD protection
    Gao, Yuexin
    Cai, Xiaowu
    Han, Zhengsheng
    Zeng, Chuanbin
    Xia, Ruirui
    Tang, Yun
    Gao, Mali
    Li, Bo
    MICROELECTRONICS RELIABILITY, 2023, 140
  • [38] Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology
    Chen, Shih-Hung
    Ker, Ming-Dou
    IPFA 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2007, : 245 - +
  • [39] Ultra-Low-Voltage-Triggered Silicon Controlled Rectifier ESD Protection Device for 2.5 V Nano Integrated Circuit
    Chen, Ruibo
    Wei, Hao
    Liu, Hongxia
    Liu, Zhiwei
    Chen, Yaolin
    NANOMATERIALS, 2022, 12 (23)
  • [40] Bidirectional Diode-Triggered Silicon-Controlled Rectifiers for Low-Voltage ESD Protection
    Liu, Wen
    Liou, Juin J.
    Yeh, Han-Chih
    Wang, Huei
    Li, You
    Yeo, Kiat Seng
    IEEE ELECTRON DEVICE LETTERS, 2012, 33 (10) : 1360 - 1362
12345