DNW-Controllable Triggered Voltage of the Integrated Diode Triggered SCR (IDT-SCR) ESD Protection Device

被引：0
|
作者：
Lai, Da-Wei [1 ]
Tseng, Wei-Jhih [1 ]
de Raad, Gijs [1 ]
Smedes, Theo [1 ]
机构：
[1] NXP Semicond, Gerstweg 2, NL-6534 AE Nijmegen, Netherlands
来源：
2017 39TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD) | 2017年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel Integrated Diode Triggered SCR (IDT-SCR), with low capacitance (<200fF), and a controllable V-T1 is proposed for 1.8V application. The triggering is determined by the DNW biasing plus one integrated diode. The fail-current density is 16 times higher, and leakage 20 times lower, compared to a traditional capacitive-triggered bigFET.
引用
收藏
页数：9
相关论文
共 50 条
  • [21] The Novel SCR-Based ESD Protection Device with High Holding Voltage
    Won, Jong-Il
    Shin, Samuell
    Ha, Ka-San
    Kwon, Jong-Ki
    Koo, Yong-Seo
    ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 1779 - +
  • [22] π-SCR Device for Broadband ESD Protection in Low-Voltage CMOS Technology
    Lin, Chun-Yu
    Lai, Yu-Hsuan
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (09) : 4107 - 4110
  • [23] Analysis and Modeling of a Low Voltage Triggered SCR ESD Protection Clamp with the Very Fast Transmission Line Pulse Measurement
    Park, Jae-Young
    Song, Jong-Kyu
    Jang, Chang-Soo
    Son, Young-Sang
    Kim, Dae-Woo
    PROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010), 2010, : 206 - 210
  • [24] Latchup-free ESD protection design with complementary substrate-triggered SCR devices
    Ker, MD
    Hsu, KC
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (08) : 1380 - 1392
  • [25] Improved Low-Voltage-Triggered SCR Structure for RF-ESD Protection (vol 34, pg 1050, 2013)
    Ma, Fei
    Han, Yan
    Dong, Shurong
    Miao, Meng
    Liang, Hailiang
    IEEE ELECTRON DEVICE LETTERS, 2013, 34 (09) : 1199 - 1199
  • [26] Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies
    Mergens, MPJ
    Russ, CC
    Verhaege, KG
    Armer, J
    Jozwiak, PC
    Mohn, RP
    Keppens, B
    Trinh, CS
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (03) : 532 - 542
  • [27] A gate-controllable high-voltage SCR device with high performance in ESD protection and latch-up immunity
    Chien, Tuo-Hsin
    Hsu, Klaus Y-J.
    ISPSD 08: PROCEEDINGS OF THE 20TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS, 2008, : 131 - 132
  • [28] A gate-controllable high-voltage SCR device with high performance in ESD protection and latch-up immunity
    Chien, Tuo-Hsin
    Hsu, Klaus Y-J.
    2008 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 46TH ANNUAL, 2008, : 629 - 630
  • [29] SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
    Ker, MD
    Hsu, KC
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2003, 3 (03) : 58 - 68
  • [30] Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process
    Ker, MD
    Hsu, KC
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (02) : 397 - 405
12345