An Architecture and an FPGA Prototype of a Reliable Processor Pipeline Towards Multiple Soft- and Timing Errors

被引：0

作者：

Bouajila, Abdelmajid ^{[1
]}

Zeppenfeld, Johannes ^{[1
]}

Stechele, Walter ^{[1
]}

Herkersdorf, Andreas ^{[1
]}

机构：

[1] Tech Univ Munich, Inst Integrated Syst, D-80290 Munich, Germany

来源：

2011 IEEE 14TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS (DDECS) | 2011年

关键词：

SYSTEMS; IMPLEMENTATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a reliable processor pipeline architecture resilient to multiple soft-and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor pipeline has low performance overheads (relative CPI of 1.06 at an error injection rate of 3 %) and is therefore much better than techniques based on flushing.

引用

页码：225 / 230

页数：6

共 12 条

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