An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA

To reduce the code size of application programs for RISC-V soft processors on an FPGA, it is desirable for the processor to support the RISC-V compressed instruction extension. In this paper, we implement an efficient instruction fetch unit. We clarify the problem of instruction fetching in pipelining processors that support the extension. To solve the problem of instruction fetching, we propose two instruction fetch units using a decompressed cache and a compressed cache, respectively. We implement the proposed fetch units and evaluate their performance, hardware resources, and operating frequency. Through the evaluation, we show that the proposed unit with a compressed cache is the best and achieves 21.8% better fetch performance using reasonable hardware resources than the baseline architecture.