Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm

In this paper a pipelined architecture of a high speed network security processor (NSP) for SSL/TLS protocol is implemented on a system on chip (SoC) where hardware information of all encryption, hashing and key exchange algorithms are stored in Secure Digital (SD) card in terms of bit files, in contrary to recent ones where all are actually implemented in hardware. The SoC works as NSP for the system (PC), which is running the application. Through the SoC the security algorithms are implemented and it also provides the Ethernet communication interface. The NSP finds applications in e-commerce, virtual private network (VPN) and in other fields that require data confidentiality. The motivation of the present work is to dynamically execute applications in embedded systems having strict resource and power budgets maintaining a stipulated throughput. An appropriate cipher suite is chosen following a proposed preferential algorithm based on Efficient System Index (ESI) budget comprising of throughput, power and resource given by the user. The bit files of the chosen security algorithms are downloaded from the SD card to the partial region of Field Programmable Gate Array (FPGA). The proposed SoC controls data communication between an application running in a system through a PCI and an Ethernet interface of a network. The proposed design uses partial reconfiguration feature of ISE14.4 suite with ZYNQ 7z020-c1g484 FPGA platform. The performances of the implemented crypto algorithms are considerably better in terms of power throughput and resource than the existing works reported in literatures. (C) 2015 Elsevier B.V. All rights reserved.