Immuno-repairing of FPGA designs

FPGAs can be used for the design of autonomic reliable systems. Advantages are reconfiguration and flexibility in the design. However commercial FPGAs are first prone to errors. Second, the design flow is not yet supported for the use of fault tolerance techniques like Built-In Self-Tests. Fault tolerance can be reached through error detection and fault recovery. Most error detection techniques are not suitable for on-line detection because of detection times and long and inflexible training. This paper proposes a fault tolerant design for FPGAs. It has a Built-In Self-Test which error evaluation and fault recovery is supported by computing techniques inspired in the Immune System. A fault recovery and a hardware implementation model are also to be presented.