Efficient Window-Architecture Design using Completely Scaling-Free CORDIC Pipeline

Filtering being one of the most important modules in signal processing paradigm, this paper presents an FPGA implementation of various window-functions using CORDIC algorithm to minimize area-delay product. The existing window-architecture uses a linear CORDIC processor in series with circular CORDIC processor, that results in a long pipeline. Firstly, we replace the linear CORDIC with multiple optimized shift-add networks to reduce area and pipeline depth. Secondly, the conventional circular CORDIC processor is replaced by a completely scaling-free CORDIC processor to further improve the area-time efficiency of the existing design. As a result, the proposed window-architecture, on an average requires approximately 64.34% less pipeline stages and saves upto 48% area. Both the existing and the proposed window-architecture are capable of generating Hanning, Hamming and Blackman window families.