Escape Routing for Staggered-Pin-Array PCBs

被引：14
|
作者：
Ho, Yuan-Kai [1 ]
Lee, Hsu-Chieh [1 ]
Chang, Yao-Wen [1 ,2 ,3 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 106, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 106, Taiwan
[3] Acad Sinica, Res Ctr Informat Technol Innovat, Taipei 115, Taiwan
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2013年 / 32卷 / 09期
关键词：
Linear programming; physical design; printed circuit board; routing; ALGORITHMS;
D O I：
10.1109/TCAD.2013.2259539
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
To accommodate the ever-growing pin number of complex printed circuit board (PCB) designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. A linear programming/integer linear programming-based algorithm is presented to solve the staggered-pin-array escape routing problem. Experimental results show that our approach successfully routes all test cases efficiently and effectively.
引用
收藏
页码：1347 / 1356
页数：10
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