Reducing power dissipation during at-speed test application

被引：2
|
作者：
Li, XW [1 ]
Li, HW [1 ]
Min, YH [1 ]
机构：
[1] Chinese Acad Sci, Inst Comp Technol, Beijing 100080, Peoples R China
来源：
2001 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2001年
关键词：
at-speed test; power dissipation; test-pair ordering;
D O I：
10.1109/DFTVS.2001.966760
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present an approach to reducing power dissipation during at-speed test application. Based on re-ordering of the test-pair sequences. the switching activities of the circuit-under-test during test application can be minimized. Hamming distance between test-pair is defined to guide test-pair re-ordering. It minimizes power dissipation during test application without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of power dissipation during test application in the range from 84.69 to 98.08%.
引用
收藏
页码：116 / 121
页数：6
相关论文
共 50 条
  • [1] Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test
    Ko, Ho Fai
    Nicolici, Nicola
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (11) : 2092 - 2097
  • [2] Reducing Power Dissipation in SRAM during Test
    Dilillo, Luigi
    Rosinger, Paul
    Al-Hashimi, Bashir M.
    Girard, Patrick
    [J]. JOURNAL OF LOW POWER ELECTRONICS, 2006, 2 (02) : 271 - 280
  • [3] A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing
    Valka, M.
    Bosio, A.
    Dilillo, L.
    Girard, P.
    Pravossoudovitch, S.
    Virazel, A.
    Sanchez, E.
    De Carvalho, M.
    Reorda, M. Sonza
    [J]. 2011 16TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2011, : 153 - 158
  • [4] Low Capture Power At-Speed Test in EDT Environment
    Moghaddam, Elham K.
    Rajski, Janusz
    Reddy, Sudhakar. M.
    Lin, Xijiang
    Mukherjee, Nilanjan
    Kassab, Mark
    [J]. INTERNATIONAL TEST CONFERENCE 2010, 2010,
  • [5] An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
    Mozaffari, Seyed Nima
    Bhaskaran, Bonita
    Narayanun, Kaushik
    Abdollahian, Ayub
    Pagalone, Vinod
    Sarangi, Shantanu
    Colburn, Jonathon E.
    [J]. 2019 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2019,
  • [6] Reducing power dissipation during test using scan chain disable
    Sankaralingam, R
    Pouya, B
    Touba, NA
    [J]. 19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2001, : 319 - 324
  • [7] On Pinpoint Capture Power Management in At-Speed Scan Test Generation
    Wen, X.
    Nishida, Y.
    Miyase, K.
    Kajihara, S.
    Girard, P.
    Tehranipoor, M.
    Wang, L. -T.
    [J]. PROCEEDINGS INTERNATIONAL TEST CONFERENCE 2012, 2012,
  • [8] Embedded at-speed test probe
    Aigner, M
    [J]. ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, : 932 - 937
  • [9] At-Speed Path Delay Test
    Chakraborty, Swati
    Walker, D. M. H.
    [J]. 2015 IEEE 24TH NORTH ATLANTIC TEST WORKSHOP (NATW), 2015, : 39 - 42
  • [10] Achieving at-speed structural test
    Pateras, S
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 2003, 20 (05): : 26 - 33
12345