Reducing power dissipation during at-speed test application

被引：2
|
作者：
Li, XW [1 ]
Li, HW [1 ]
Min, YH [1 ]
机构：
[1] Chinese Acad Sci, Inst Comp Technol, Beijing 100080, Peoples R China
来源：
2001 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2001年
关键词：
at-speed test; power dissipation; test-pair ordering;
D O I：
10.1109/DFTVS.2001.966760
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present an approach to reducing power dissipation during at-speed test application. Based on re-ordering of the test-pair sequences. the switching activities of the circuit-under-test during test application can be minimized. Hamming distance between test-pair is defined to guide test-pair re-ordering. It minimizes power dissipation during test application without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of power dissipation during test application in the range from 84.69 to 98.08%.
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页码：116 / 121
页数：6
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