Investigation on Body Potential in Cylindrical Gate-All- Around MOSFET

被引:0
|
作者
Kessi, M. [1 ]
Benfdila, A. [1 ]
Lakhelef, A. [1 ]
Belhimer, L. [1 ]
Djouder, M. [1 ]
机构
[1] Univ M Mammeri, Micro & Nanotechnol Res Grp MNRG, Fac Elect Engn & Comp Sci, UMMTO DZ, Tizi Ouzou 15000, Algeria
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Cylindrical gate all around (CGAA) MOSFET has been studied and the body potential has been simulated and studied. The center and surface potentials models are studied and a comparison is made between the two potential behaviours for a CGAA MOSFET. Moreover, the channel doping concentration and the band diagrams are obtained using the Finite element numerical method by solving poisson's equation in the cylindrical coordinate system.
引用
收藏
页码:213 / 216
页数:4
相关论文
共 50 条
  • [21] Journey of MOSFET from Planar to Gate All Around: A Review
    Bhol, Krutideepa
    Jena, Biswajit
    Nanda, Umakanta
    RECENT PATENTS ON NANOTECHNOLOGY, 2022, 16 (04) : 326 - 332
  • [22] Modeling of gate leakage in cylindrical gate-all-around transistors
    Ravi Solanki
    Saniya Minase
    Ashutosh Mahajan
    Rajendra Patrikar
    Journal of Computational Electronics, 2021, 20 : 1694 - 1701
  • [23] Modeling of gate leakage in cylindrical gate-all-around transistors
    Solanki, Ravi
    Minase, Saniya
    Mahajan, Ashutosh
    Patrikar, Rajendra
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2021, 20 (05) : 1694 - 1701
  • [24] Analytical Model and Performance Investigation of Electric Potential for Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET
    Abhinav
    Srivastava, Manish
    Kumar, Amrish
    Rai, Sanjeev
    2017 4TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN), 2017, : 256 - 261
  • [25] Novel design to improve band to band tunneling and gate induced drain leakages (GIDL) in cylindrical gate all around (GAA) MOSFET
    Rewari, Sonam
    Nath, Vandana
    Haldar, Subhasis
    Deswal, S. S.
    Gupta, R. S.
    MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2019, 25 (05): : 1537 - 1546
  • [26] Gate-Induced Drain Leakage Reduction in Cylindrical Dual-Metal Hetero-Dielectric Gate All Around MOSFET
    Rewari, Sonam
    Nath, Vandana
    Haldar, Subhasis
    Deswal, S. S.
    Gupta, R. S.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (01) : 3 - 10
  • [27] Novel design to improve band to band tunneling and gate induced drain leakages (GIDL) in cylindrical gate all around (GAA) MOSFET
    Sonam Rewari
    Vandana Nath
    Subhasis Haldar
    S. S. Deswal
    R. S. Gupta
    Microsystem Technologies, 2019, 25 : 1537 - 1546
  • [28] Investigation of analog/RF performance of gate-all-around junctionless MOSFET including interfacial defects
    Ferhati, H.
    Djeffal, F.
    Bentrcia, T.
    2015 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING (ICEE), 2015, : 328 - U451
  • [29] Investigation of Cylindrical Channel Gate All Around InGaAs/InP Heterojunction Heterodielectric Tunnel FETs
    Vimala, P.
    Arun Samuel, T. S.
    SILICON, 2021, 13 (11) : 3899 - 3907
  • [30] Investigation of Cylindrical Channel Gate All Around InGaAs/InP Heterojunction Heterodielectric Tunnel FETs
    P. Vimala
    T. S. Arun Samuel
    Silicon, 2021, 13 : 3899 - 3907