Novel VLSI architecture of motion estimation for H.264 standard

被引：0

作者：

Li, X ^{[1
]}

Chopra, R ^{[1
]}

Hsu, KW ^{[1
]}

机构：

[1] Rochester Inst Technol, Rochester, NY 14623 USA

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel architecture to achieve real-time motion estimation compensation encoding for H.264 ITU Video compression standard is presented. A full-search block matching algorithm has been adapted to a pipelined data flow to enable parallel processing of variable block sized block matching and fractional pixel motion vector generation. The SOC is designed with TSMC 0.18um technology using VHDL and optimized to achieve a 125 MHz clock speed to make real-time processing possible.

引用

页码：117 / 118

页数：2

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