Ultrathin Die Pick-Up for 3D Chip Stacking

被引:2
|
作者
Kawano, Masaya [1 ]
Hirota, Naoya [2 ]
Lim, Sharon Pei-Siang [1 ]
Chong, Ser-Choong [1 ]
机构
[1] ASTAR, Inst Microelect, Singapore, Singapore
[2] Fusionopolis Way,08-02 Innovis Tower, Singapore 138634, Singapore
关键词
D O I
10.1109/eptc47984.2019.9026703
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Ultrathin die pick-up is studied for 3D IC applications. Failure modes are identified as follows: 1) no pick-up due to insufficient peeling; 2) die crack created by ejector; 3) neighboring die crack due to ejector push-up. Optimal dicing tape is selected along with pick-up process tuning. By using optimal dicing tape, pick-up process window is identified for 20 and 30 mu m thickness Si die with 8x8 and 12x12 mm die size. The failure modes of "die crack created by ejector" and "neighboring die crack" occur when push height is large and/or pickp-up time is short. The failure mode of "no pick-up" occurs at insufficient push height. Finally, pick-up conditions with 100% yield are identified with <= 1 sec pick-up time.
引用
收藏
页码:171 / 174
页数:4
相关论文
共 50 条
  • [21] Application of 3D glycerol-compensated inclined-exposure technology to an integrated optical pick-up head
    Hung, KY
    Hu, HT
    Tseng, FG
    JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2004, 14 (07) : 975 - 983
  • [22] 3D chip stacking with C4 technology
    Dang, B.
    Wright, S. L.
    Andry, P. S.
    Sprogis, E. J.
    Tsang, C. K.
    Interrante, M. J.
    Webb, B. C.
    Polastre, R. J.
    Horton, R. R.
    Patel, C. S.
    Sharma, A.
    Zheng, J.
    Sakuma, K.
    Knickerbocker, J. U.
    IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2008, 52 (06) : 599 - 609
  • [23] 3-D Stacking of Ultrathin Chip Packages: An Innovative Packaging and Interconnection Technology
    Priyabadini, Swarnakamal
    Sterken, Tom
    Van Hoorebeke, Luc
    Vanfleteren, Jan
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (07): : 1114 - 1122
  • [24] Processor design in 3D die-stacking technologies
    Loh, Gabriel H.
    Xie, Yuan
    Black, Bryan
    IEEE MICRO, 2007, 27 (03) : 31 - 48
  • [25] Heterogeneous Integration by the 3D Stacking of Thin Silicon Die
    Nittala, Pavani Vamsi Krishna
    Haridas, Karthika
    Sen, Prosenjit
    IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022), 2022, : 608 - 613
  • [26] THIN DIE STACKING TECHNOLOGIES FOR 3D MEMORY PACKAGES
    Wu, Jie
    Yauw, Oranna
    Tan, Andrew
    Clauberg, Horst
    Buergi, Daniel
    2018 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2018,
  • [27] A 3D FPGA architecture to realize simple die stacking
    Amagasaki, Motoki
    Zhao, Qian
    Iida, Masahiro
    Kuga, Morihiro
    Sueyoshi, Toshinori
    IPSJ Transactions on System LSI Design Methodology, 2015, 8 : 116 - 122
  • [28] Foundry TSV Enablement For 2.5D/3D Chip Stacking
    Yu, Remi
    2012 IEEE HOT CHIPS 24 SYMPOSIUM (HCS), 2012,
  • [29] Stress Analysis for Silicon Die Pick-up Process Through Finite Element Analysis
    Kim, Seungbin
    Lee, Yong-Seok
    TRANSACTIONS OF THE KOREAN SOCIETY OF MECHANICAL ENGINEERS A, 2023, 47 (09) : 695 - 700
  • [30] Characterization of Dicing Tape Adhesion for Ultra-thin Die Pick-up Process
    Chan, Y. Sing
    Chew, Julie
    Goh, Chu Hua
    Chua, Siang Kuan
    Yeo, Alfred
    2014 IEEE 16TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2014, : 554 - 557