A 97.99 dB SNDR, 2 kHz BW, 37.1 μW Noise-Shaping SAR ADC with Dynamic Element Matching and Modulation Dither Effect

被引：69
|
作者：
Obata, Koji [1 ]
Matsukawa, Kazuo [1 ]
Miki, Takuji [1 ]
Tsukamoto, Yusuke [1 ]
Sushihara, Koji [1 ]
机构：
[1] Panasonic Corp, Osaka, Japan
来源：
2016 IEEE SYMPOSIUM ON VLSI CIRCUITS (VLSI-CIRCUITS) | 2016年
关键词：
SAR ADC; Sigma modulation; Noise-shaping and Dynamic element matching (DEM);
D O I：
10.1109/VLSIC.2016.7573463
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 97.99 dB SNDR, 2 kHz bandwidth noise-shaping SAR ADC was fabricated in 28 nm CMOS process. By integrating residue of 12 bit SAR AD conversion with 3rd order integrator, S modulation is achieved and noise floor of AD conversion is shaped. Distortion due to mismatch of capacitive DAC is eliminated by introducing dynamic element matching (DEM) technique and by utilizing modulation dither effect. The ADC consumes 37.1 mu W with 100 kHz sampling speed and achieves Schreier's figure of merit (FoMs) of 175.3 dB.
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