A 1.25-MHz-BW, 83-dB SNDR Pipelined Noise-Shaping SAR ADC With MASH 2-2 Structure and kT/C Noise Cancellation

This brief presents a 4(th)-order noise-shaping (NS)successive approximation register (SAR) analog-to-digital con-verter (ADC) using a 2-2 multistage noise-shaping (MASH)structure. By combining pipeline timing with kT/C noise cancella-tion and dynamic amplifier (DA) sharing techniques, a high-ordernoise-shaping SAR with reduced hardware cost and optimizedtiming is achieved. Fabricated in a 65-nm CMOS technology,the prototype NS-SAR ADC consumes 335 mu W under a 1.2-Vsupply voltage when operating at a 20-MS/s sampling rate. An83-dB signal-to-noise-and-distortion ratio (SNDR) is measuredfor a 0.367-MHz sinusoid input under an oversampling ratio(OSR) of 8. It achieves a peak Schreier FoM of 178 dB and thecore circuit occupies a 0.08-mm(2)area