On-chip signal level evaluation for mixed-signal ICs using digital window comparators

被引：0
|
作者：
De Venuto, D [1 ]
Ohletz, MJ [1 ]
Ricco, B [1 ]
机构：
[1] Politecn Bari, Dipartimento Elettrotecn & Elettron, Bari, Italy
来源：
ETW 2001: IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS | 2001年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The possibility of using window comparators for on-chip (and potentially on-line) response evaluation of analogue circuits is investigated. No additional analogue test inputs are required and the additional circuitry can be realised either by means of standard digital gates taken from an available library or by full custom designed gates to obtain an observation window tailored on by the application. With this approach, test overhead can be kept extremely low. Due to the low gate capacitance also the load on the observed nodes is very low. Simulation results for some examples show that 100% of all assumed layout-realistic faults could be detected.
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收藏
页码：68 / 72
页数：5
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