Rounding Technique Analysis for Power-Area & Energy Efficient Approximate Multiplier Design

被引:0
|
作者
Lohray, Priyanka [1 ]
Gali, Satwik [1 ]
Rangisetti, Srirathan [1 ]
Nikoubin, Tooraj [1 ]
机构
[1] Texas Tech Univ, Elect & Comp Engn Dept, Lubbock, TX 79409 USA
关键词
Data Processing; Digital Arithmetic; Approximate computing; Energy efficient; Hi-performance; Rounding Technique;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Approximate computing is one of best suited efficient data processing for error resilient applications, such as signal and image processing, computer vision, machine learning, data mining etc. Approximate computing reduces accuracy which is acceptable as a cost of increasing the circuit characteristics depends on the application. Desirable accuracy is the threshold point for controlling the trade off, between accuracy and circuit characteristics under the control of the circuit designer. In this work, the rounding technique is introduced as an efficient method for controlling this trade off. In this regard multiplier circuits as a critical building block for computing in most of the processors have been considered for the evaluation of the rounding technique efficiency. The impact of the rounding method is investigated by comparison of circuit characteristics for three multipliers. These three multipliers are the conventional Wallace tree accurate multiplier, DRUM [4] the recently proposed approximate multiplier and the rounded based approximate multiplier proposed in this work. Simulation results for three selected technologies show significant improvement on the circuit characteristics in terms of power, area, speed, and energy for proposed multiplier in comparison with their counterparts. Input data rounding pattern and the probability of the repetition for rounded values has been introduced as two essential items to control the level of the accuracy for each range of the data with minimum cost on the hardware.
引用
收藏
页码:420 / 425
页数:6
相关论文
共 50 条
  • [31] Design of an area-efficient multiplier
    Kumar, Naman S.
    Shravan, S. D.
    Sudhanva, N. G.
    Hande, Shreyas V.
    Kumar, Praveen Y. G.
    2017 INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN ELECTRONICS AND COMMUNICATION TECHNOLOGY (ICRAECT), 2017, : 329 - 332
  • [32] Power And Delay Efficient Exact Adder For Approximate Multiplier
    Kavipranesh, V. V.
    Janarthanan, J.
    Amruth, Naga T.
    Harisuriya, T. M.
    Prabhu, E.
    2018 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2018, : 1896 - 1899
  • [33] Truncation and Rounding-Based Scalable Approximate Multiplier Design for Computer Imaging Applications
    Rooban, S.
    Ratnam, A. Yamini Naga
    Ramprasad, M. V. S.
    Subbulakshmi, N.
    Mageswari, R. Uma
    CMC-COMPUTERS MATERIALS & CONTINUA, 2022, 73 (03): : 5169 - 5184
  • [34] An Energy Efficient 32 Bit Approximate Dadda Multiplier
    Chanda, Saurav
    Guha, Koushik
    Patra, Santu
    Singh, Loukrakpam Merin
    Baishnab, Krishna Lal
    Paul, Prashanta Kumar
    2020 IEEE CALCUTTA CONFERENCE (CALCON), 2020, : 162 - 165
  • [35] Comparison and design of energy-efficient approximate multiplier schemes for image processing by CNTFET
    Tavakkoli, Elmira
    Shokri, Shayan
    Aminian, Mahdi
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2024, 111 (05) : 813 - 834
  • [36] Area Efficient High Speed Approximate Multiplier with Carry Predictor
    Sunny, Anju
    Mathew, Binu K.
    Dhanusha, P. B.
    INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING, SCIENCE AND TECHNOLOGY (ICETEST - 2015), 2016, 24 : 1170 - 1177
  • [37] Design of Power Efficient Posit Multiplier
    Zhang, Hao
    Ko, Seok-Bum
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (05) : 861 - 865
  • [38] Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method
    Yang, Tongxin
    Ukezono, Tomoaki
    Sato, Toshinori
    GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI, 2019, : 39 - 44
  • [39] Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full-swing GDI technique
    Albadry, Omnia Ali
    El-Bendary, M. A. Mohamed
    Amer, Fathy Z.
    Singy, Said M.
    PROCEEDINGS OF 2019 INTERNATIONAL CONFERENCE ON INNOVATIVE TRENDS IN COMPUTER ENGINEERING (ITCE 2019), 2019, : 328 - 333
  • [40] Design of Energy Efficient Posit Multiplier
    Jonnalagadda, Aditya Anirudh
    Uppugunduru, Anil Kumar
    Veeramachaneni, Sreehari
    Ahmed, Syed Ershad
    PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2023, GLSVLSI 2023, 2023, : 645 - 651