Automated Diagnosis of HV/LV and Floating Gate Faults in VLSI Design

被引：0
|
作者：
Zhu, Qing K. [1 ]
机构：
[1] Int Technol Univ, Elect Engn Dept, 355 W San Fernando St, San Jose, CA 95113 USA
来源：
PROCEEDINGS OF THE 24TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS - MIXDES 2017 | 2017年
关键词：
VLSI; Design; Multiple voltages; HV/LV; Floating gate; CAD; Tapeout;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents automated methods and CAD programs to trace the connectivity of hierarchical netlists and detect HV/LV connection or floating gate faults in VLSI design. We describe algorithms and data structures for the flattening of a hierarchical netlist as well as detecting faults in a large circuit. The paper describes experimental results and GUI capability to highlight faults in Cadence schematic window.
引用
收藏
页码：229 / 233
页数：5
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