Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI

被引：2

作者：

Tongprasit, Benjamas ^{[1
]}

Shibata, Tadashi ^{[1
]}

机构：

[1] Univ Tokyo, Dept Frontier Informat, Tokyo, Japan

来源：

2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/ISCAS.2006.1693718

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Design and experimental evaluation of power-balanced reconfigurable floating-gate-MOS logic circuit is presented. The circuit can represent all 512 symmetric Boolean functions for eight inputs and 256 Boolean functions for three-input symmetric/asymmetric functions. The programming of function is done by control signals. Namely, no change in hardware configuration is required. The proposed circuit employs a highly symmetric architecture. The input data and the control signals are broadcasted in pairs with their complementary values. As a result, the power consumption of the circuit is independent of the input data and the logic function. Hence, the proposed circuit is resistant to the power analysis attack.

引用

页码：4855 / +

页数：2

共 7 条

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