Efficient FPGA implementation of modular multiplication based on Montgomery algorithm

被引：8
|
作者：
Yang, Yatao [1 ]
Wu, Chao [2 ]
Li, Zichen [1 ,3 ]
Yang, Junming [1 ]
机构：
[1] Beijing Elect Sci & Technol Inst, Beijing 100070, Peoples R China
[2] UTEK TECHNOL SHENZHEN CO LTD, Shenzhen 518000, Peoples R China
[3] Beijing Inst Graph Commun, Beijing 102600, Peoples R China
来源：
MICROPROCESSORS AND MICROSYSTEMS | 2016年 / 47卷
基金：
中国国家自然科学基金;
关键词：
Montgomery modular multiplication; FPGA; Multiplier IP cores; Addition IP cores; CURVE CRYPTOGRAPHY PROCESSOR; HIGH-THROUGHPUT;
D O I：
10.1016/j.micpro.2016.07.008
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In order to improve the efficiency of modular multiplication algorithm for FPGA implementation on the prime field modular, an efficient scheme is proposed to accomplish 256 x 256 bits modular multiplication algorithm. The embedded IP cores of Xilinx FPGA are efficiently utilized to design 512-bit addition and 256 x 256 bits multiplier. Moreover, the above modules are used to complete Montgomery modular multiplication algorithm. Compared with traditional implementation method, almost 50% running efficiency is improved in our scheme, which has important value to implement complicated cryptographic processor in hardware environment. (C) 2016 Elsevier B.V. All rights reserved.
引用
收藏
页码：209 / 215
页数：7
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