Pin Multiplexing Optimization in FPGA Prototyping System

FPGA partition is a key step to prototype a complex ASIC design onto multi-FPGA system. After partitioning, due to the number of inter-FPGA signals is much greater than that of physical connections available on the board, FPGA pin multiplexing technique is then introduced. It's believed that pin multiplexing strategy directly affects the timing performance of the whole FPGA prototyping system. In the present work, pin multiplexing optimization is implemented based on a new proposed system-synchronous architecture. At the same time, the protocol converter module is developed to make ASIC design interface more compatible to the different handshake protocols. Experiments are done in a multi-FPGA board with two test pattern SHR and PRBS. As a result, system performance of the present architecture is compared with two traditional methods. Test data show that timing performance of the System-synchronous approach doubled than I/OSERDES approach and even much more than Logic TDM.