Delay-Insensitive Asynchronous ALU for Cryogenic Temperature Environments

被引:12
|
作者
Hollosi, Brent [1 ]
Barlow, Matthew [2 ]
Fu, Guoyuan [2 ]
Lee, Chris [2 ]
Di, Jia [1 ]
Smith, Scott C. [2 ]
Mantooth, H. Alan [2 ]
Schupbach, Marcelo [3 ]
机构
[1] Univ Arkansas, Dept Comp Sci & Comp Engn, Fayetteville, AR 72701 USA
[2] Univ Arkansas, Dept Elect Engn, Fayetteville, AR 72701 USA
[3] Arkansas Power Elect Int Inc, Fayetteville, AR 72701 USA
关键词
D O I
10.1109/MWSCAS.2008.4616801
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper details the design and performance of a delay-insensitive asynchronous 8-bit ALU for an asynchronous 8051-compliant microcontroller intended for extreme environments. The ALU was designed using a quasi-delay-insensitive logic called NULL Convention Logic (NCL), in order to allow for reliable circuit operation over a wide temperature range and enable extreme supply voltage scaling for low power consumption. The ALU was fabricated along with several other 8051-essential components at MOSIS using the IBM SiGe5AM 0.5 mu m process. A series of tests at both room and cryogenic temperatures has been performed, which has demonstrated that the designed ALU is able to operate correctly from 2K (-271 degrees C) to 297K (23 degrees C), as well as over wide supply voltage variations.
引用
收藏
页码:322 / +
页数:2
相关论文
共 50 条
  • [1] Delay-insensitive computation in asynchronous cellular automata
    Lee, J
    Adachi, S
    Peper, F
    Mashiko, S
    [J]. JOURNAL OF COMPUTER AND SYSTEM SCIENCES, 2005, 70 (02) : 201 - 220
  • [2] Diagrammatic reasoning for delay-insensitive asynchronous circuits
    [J]. Ghica, D.R., 1600, Springer Verlag (7860 LNCS):
  • [3] Quasi delay-insensitive bus for fully asynchronous systems
    Molina, PA
    Cheung, PYK
    Bormann, DS
    [J]. ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 189 - 192
  • [4] A quasi delay-insensitive bus proposal for asynchronous systems
    Molina, PA
    Cheung, PYK
    [J]. THIRD INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 1997, : 126 - 139
  • [5] Embedding universal delay-insensitive circuits in asynchronous cellular spaces
    Lee, J
    Adachi, S
    Peper, F
    Morita, K
    [J]. FUNDAMENTA INFORMATICAE, 2003, 58 (3-4) : 295 - 320
  • [6] Asynchronous comparison-based decoders for delay-insensitive codes
    Akella, V
    Vaidya, NH
    Redinbo, GR
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1998, 47 (07) : 802 - 811
  • [7] New ternary data encoding for delay-insensitive asynchronous design
    [J]. 1600, Science and Engineering Research Support Society, 20 Virginia Court, Sandy Bay, Tasmania, Australia (07):
  • [8] An Automated Design Flow Framework for Delay-Insensitive Asynchronous Circuits
    Thian, Ross
    Caley, Landon
    Arthurs, Aaron
    Hollosi, Brent
    Di, Jia
    [J]. 2012 PROCEEDINGS OF IEEE SOUTHEASTCON, 2012,
  • [9] Verification and implementation of delay-insensitive processes in restrictive environments
    Kapoor, HK
    Josephs, MB
    Furey, DP
    [J]. FOURTH INTERNATIONAL CONFERENCE ON APPLICATION OF CONCURRENCY TO SYSTEM DESIGN, PROCEEDINGS, 2004, : 89 - 98
  • [10] On the realisation of delay-insensitive asynchronous circuits with CMOS ternary logic
    Mariani, R
    Roncella, R
    Saletti, R
    Terreni, P
    [J]. THIRD INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 1997, : 54 - 62