An efficient system-level to RTL verification framework for computation-intensive applications

被引:2
|
作者
Liveris, ND [1 ]
Zhou, H [1 ]
Banerjee, P [1 ]
机构
[1] Northwestern Univ, Evanston, IL 60208 USA
关键词
D O I
10.1109/ATS.2005.24
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper a new framework for formal verification is presented. The new framework called EVRM (Efficient VeRfication based on Mathematica [1]) can be used for the property verification of a Register Transfer Level implementation using a System Level description as the golden model. EVRM is based on word level techniques and uses the Mathematica tool for the satisfiability procedure. Results show that it can be orders of magnitude faster than CBMC [2] in proving property correctness or providing a counterexample for computation-intensive applications. For certain applications CBMC requires more than 5 hours to provide an answer while EVRM provides an answer in less than 10 minutes.
引用
收藏
页码:28 / 33
页数:6
相关论文
共 50 条
  • [21] TIMING VERIFICATION FOR SYSTEM-LEVEL DESIGNS
    CHIANG, M
    BLOOM, M
    VLSI SYSTEMS DESIGN, 1987, 8 (13): : 46 - +
  • [22] Heuristic Offloading of Concurrent Tasks for Computation-Intensive Applications in Mobile Cloud Computing
    Jia, Mike
    Cao, Jiannong
    Yang, Lei
    2014 IEEE CONFERENCE ON COMPUTER COMMUNICATIONS WORKSHOPS (INFOCOM WKSHPS), 2014, : 352 - 357
  • [23] Leveraging sequential equivalence checking to enable system-level to RTL flows
    Urard, Pascal
    Maalej, Asma
    Guizzetti, Roberto
    Chawla, Nitin
    Krishnaswamy, Venkatram
    2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 816 - 821
  • [24] A Verification Approach for System-Level Concurrent Programs
    Daum, Matthias
    Doerrenbaecher, Jan
    Schmidt, Mareike
    Wolff, Burkhart
    VERIFIED SOFTWARE: THEORIES, TOOLS, EXPERIMENTS, 2008, 5295 : 161 - 176
  • [25] A scheduling framework for system-level estimation
    Le Moullec, Y
    Diguet, JP
    Philippe, JL
    ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II, 2000, : 277 - 280
  • [26] Efficient In-System RTL Verification and Debugging Using FPGAs
    Saha, Proshanta
    Haymes, Chuck
    Bellofatto, Ralph
    Brezzo, Bernard
    Kapur, Mohit
    Asaad, Sameh
    FPGA 12: PROCEEDINGS OF THE 2012 ACM-SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, 2012, : 269 - 269
  • [27] Framework Development for Efficient Mission-Oriented Satellite System-Level Design
    Kwon, Kybeom
    Min, Seunghyun
    Kim, Jongbum
    Lee, Kwangwon
    AEROSPACE, 2023, 10 (03)
  • [28] System-level State Equality Detection for the Formal Dynamic Verification of Legacy Distributed Applications
    Guthmuller, Marion
    Quinson, Martin
    Corona, Gabriel
    23RD EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP 2015), 2015, : 451 - 458
  • [29] Efficient System-Level Aging Prediction
    Hatami, Nadereh
    Baranowski, Rafal
    Prinetto, Paolo
    Wunderlich, Hans-Joachim
    2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2012,
  • [30] System-level state equality detection for the formal dynamic verification of legacy distributed applications
    Guthmuller, Marion
    Corona, Gabriel
    Quinson, Martin
    JOURNAL OF LOGICAL AND ALGEBRAIC METHODS IN PROGRAMMING, 2018, 96 : 1 - 11